EE Times -IBM, Sony, Toshiba team on processor architecture for broadband

Good summary of the information currently available on the proposed 'cell' processor. Looks like the idea is to shrink down a SGI MIPS cluster down to a system-on-chip size. Basically looking for increased performance through massively parrallel processing. Funnily enough it's similar to the work I'm doing, with interconnected processor cores on a single chip, in my case an FPGA is used and the purpose is to simulate graph problems. But the cell chip aims to use a similar layout to do calculations optimized for handling multimedia-heavy network traffic (for use inside routers). Neat stuff, if and when it comes to fruition.

According to El Reg, Initial sampling has begun. Now I wanna get a board with a few of these things on there to match up their "one teraflop on a chip" claims with the harsh light of real-world constraints.